Most embedded processors are somebody else's design, licensed to you on somebody else's terms. RISC-V fundamentally tears that down, in the way Linux tore down Unix server operating systemsd. It is an open instruction-set architecture: you can build a core, drop it in an FPGA or an ASIC, and owe no per-chip license fee to anyone. That can be the difference between a viable bill of materials and a project that isn't going to make it to production. Sometimes, the money is not the point at all. The point is that you can change the processor itself. (Cue Neuromancer music.)
The ARM tax
ARM is a capable architecture that is lieterally EVERYWHERE in the world. Your phone or tablet? ARM. Most well-known SBCs and high-end SoC hardware? ARM. Embedded systems? ARM. NVidia Jetson? ARM. But you rent the ARM architecture. Every core carries the burden of a license and usually a per-unit royalty. At high volume, or on a thin-margin product, that royalty is a tax you cannot engineer your way out of. RISC-V has no such toll. The ISA is open, mature implementations are freely available, and the cores you build yourself cost you engineering effort, not royalties. When the ARM tax stops adding up, RISC-V can be the salvation.
When you need to change the processor
But the deeper reason to reach for RISC-V is customization. You cannot easily add an instruction to an ARM core. You can add one to a RISC-V core just by changing the source code. If your workload has a hot loop that a purpose-built instruction would collapse, a cryptographic primitive you want in hardware, or a domain operation that belongs in the pipeline instead of a library, RISC-V lets you extend the instruction set and build a core that runs it. We have built custom RISC-V cores on a FPGA platforms, including custom instruction-set extensions, so we know the gotchas: designing the instructions, implementing them in the core, and teaching the toolchain and software to use them. FPGAs are even runtime-reconfigurable and field-updateable. To quote TRON's Kevin Flynn, "It's digital jazz, man."
Soft cores on FPGA
A lot of this work lives in the FPGA: a soft-core RISC-V you can respin without taping out silicon, sitting next to the rest of your logic and tuned to the board and the job in front of it. That is adjacent to our safety-critical and embedded work, where the processor, the drivers, and the software all have to fit the hardware you actually have rather than the hardware you wish you had.
Let us help you get to the CORE of your problem, and then back out again, safely!
Who works on it
AlphaPixel is a US-owned small business, founded in 2004, with senior developers who work from the instruction set up through drivers and applications. DLA DD2345 / ITAR registered. Some of our RISC-V work is not publicly disclosable, so if that describes your program, we are used to working that way.
Frequently asked questions
What is RISC-V and why would I use it instead of ARM?
RISC-V is an open instruction-set architecture: you can build a core, drop it in an FPGA or an ASIC, and owe no per-chip license fee to anyone. ARM is capable and everywhere, but you rent it, and every core carries a license and usually a per-unit royalty. On a high-volume or thin-margin product that royalty is a tax you cannot engineer your way out of, and RISC-V has no such toll.
Do you build custom RISC-V cores?
Yes. We have built custom RISC-V cores on FPGA platforms, including custom instruction-set extensions, so we know the real gotchas: designing the instructions, implementing them in the core, and teaching the toolchain and software to use them.
Can you add custom instructions to a RISC-V core?
Yes, and that is often the real reason to choose RISC-V. You cannot easily add an instruction to an ARM core, but you can add one to a RISC-V core by changing the source. If you have a hot loop a purpose-built instruction would collapse, a cryptographic primitive you want in hardware, or a domain operation that belongs in the pipeline instead of a library, we can extend the ISA and build a core that runs it.
Soft core on an FPGA, or a hard core in silicon?
A lot of this work lives in the FPGA: a soft-core RISC-V you can respin without taping out silicon, sitting next to the rest of your logic and tuned to the board and the job in front of it. FPGAs are runtime-reconfigurable and field-updateable, which keeps you flexible before you commit to an ASIC.
Can RISC-V lower our bill of materials or royalty cost?
It can. The cores you build yourself cost you engineering effort, not royalties, so when the ARM royalty stops adding up RISC-V can be the difference between a viable bill of materials and a product that does not reach production. Sometimes the money is not even the point, the point is that you can change the processor itself.
Do you handle the toolchain and software for custom instructions, not just the hardware?
Yes. A custom instruction is useless if the compiler and libraries cannot reach it, so we work from the instruction set up through the drivers and the application, and we make the toolchain and software actually use the extensions we add.
Can you work on RISC-V programs that cannot be disclosed publicly?
Yes. Some of our RISC-V work is not publicly disclosable. We are a US-owned small business, DLA DD2345 and ITAR registered, and we are used to working that way.
How do we scope a RISC-V or FPGA project with you?
Tell us the platform (FPGA or ASIC path), the workload you want to accelerate, and whether the driver is cost, customization, or both. We will scope the core, the instruction extensions, and the toolchain work from there. Contact us to start.
Talk to us
Tell us what you’re building and where it’s stuck. We’ll tell you straight whether it’s something we can help with, and how we’d approach it.
Or see how we run consulting and software development engagements.
